1. Field
The embodiments relate to a designing apparatus, a designing method, and a program.
2. Description of the Related Art
FIG. 1 is a flowchart showing a procedure of a conventional digital circuit designing method. At operation S101, a digital circuit structure is analyzed on the basis of register transfer level (RTL) design data.
As shown in FIG. 1, libraries 111 and 112 are single-ended signal libraries for use in generation of netlist design data of single-ended signal cell that receive or output single-ended signal. A single-ended signal is one signal based on a reference voltage (for example, a ground voltage). The libraries 111 include a plurality of cell libraries having different transistor threshold voltages Vth. The libraries 112 include a plurality of cell libraries having different supply voltages. Different kinds of libraries are prepared according to the supply voltages and transistor threshold voltages Vth.
As further shown in FIG. 1, at operation S102, a predetermined library is selected from the plurality of libraries 111 and 112 having different supply voltages and/or different transistor threshold voltages Vth. Information of the selected library is stored.
As further shown in FIG. 1, at operation S103, logic synthesis is performed on the basis of the RTL design data using the selected library 111 or 112 to generate netlist design data 104 of single-ended signal cell.
As further shown in FIG. 1, at operation S105, timing analysis is performed on the basis of the netlist design data 104.
As further shown in FIG. 1, at operation S106, if the timing is verified to be met as a result of the timing analysis the netlist design data 107 is stored in a storage unit, and then the process is terminated. If the timing is verified not to be met as a result of the timing analysis, the process proceeds to operation S108.
As further shown in FIG. 1, at operation S108, whether to change the selected library is determined. If the selected library is determined not to be changed, the process returns to operation S103, and the logic synthesis is performed again using another cell included in the same library. If the selected library is determined to be changed, the process proceeds to operation S109.
As further shown in FIG. 1, at the operation S109, the library selected at operation S102 is excluded from selection candidates. The process then returns to operation S102. Another library is selected at operation S102, and the logic synthesis is performed again.
In analog circuits, low amplitude differential signals are used as clock signals for the purpose of high-speed operations.
Additionally, in analog circuit design, which is performed manually, a operation of converting differential signals into or from single-ended signals and a operation of converting operating voltage ranges of low amplitude differential signals are needed since the low amplitude differential signals are handled.
On the other hand, in digital circuits, single-ended signals, but not differential signals, are used when the clock frequency is low. As further shown in FIG. 1, in digital circuit design, only single-ended signal cells are designed on the basis of the single-ended signal libraries 111 and 112.
That is, logic synthesis is not performed on differential signals. When the clock frequency of digital circuits is high, the circuits are designed manually to consider interference from others, such as crosstalk.
With an increase in the operation speed of circuits, there is an increasing demand for an increase in the operation speed of circuits using low amplitude differential signals in digital circuits. In addition, treatment of low amplitude differential signals through logic synthesis based on RTL design data is desired in digital circuit design.
Since logic synthesis based on the RTL design data cannot be performed regarding digital circuits using low amplitude differential signals in the aforementioned conventional designing methods, efficient circuit design cannot be performed.